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Wafer AI - Member of Technical Staff

deCircle

Recruitee
Location
San Francisco, United States, United States
Type
Not specified
Salary
Salary not specified
Posted
12 Oct 2026
Wafer AI: maximize intelligence per watt; autonomous AI performance engineers optimizing inference on heterogeneous hardware. 7 people, $4M raised, SF. Comp: $200K-$300K + 0.5%-1% equity. Location: on-site 5 days FiDi SF. Visa: Visa transfers (H-1B transfer, OPT); must already be in US; no new H1B. Responsibilities Ship day-zero support for new open-source models tuned for latency/throughput Optimize serving stack: batching, KV cache, speculative decoding, quantization Write/tune kernels in CUDA, HIP, Triton for NVIDIA, AMD, TPU, Trainium, D-Matrix Design, deploy, operate heterogeneous multi-vendor clusters Run production inference: reliability, observability, cost per token Tech stack: CUDA, HIP, Triton, Python, TPU, AWS Trainium Source: https://www.paraform.com/share/wafer-ai/cmrtyva4m000j0cl7i7j9wbue 1-6 yrs SWE focused on systems close to hardware GPU kernels (CUDA/HIP/Triton), inference serving optimization First-principles, resourceful, high EQ; customer-facing comfort On-site 5 days SF; must be in US
Wafer AI: maximize intelligence per watt; autonomous AI performance engineers optimizing inference on heterogeneous hardware. 7 people, $4M raised, SF. Comp: $200K-$300K + 0.5%-1% equity. Location: on-site 5 days FiDi SF. Visa: Visa transfers (H-1B transfer, OPT); must already be in US; no new H1B. Responsibilities Ship day-zero support for new open-source models tuned for latency/throughput Optimize serving stack: batching, KV cache, speculative decoding, quantization Write/tune kernels in CUDA, HIP, Triton for NVIDIA, AMD, TPU, Trainium, D-Matrix Design, deploy, operate heterogeneous multi-vendor clusters Run production inference: reliability, observability, cost per token Tech stack: CUDA, HIP, Triton, Python, TPU, AWS Trainium Source: https://www.paraform.com/share/wafer-ai/cmrtyva4m000j0cl7i7j9wbue 1-6 yrs SWE focused on systems close to hardware GPU kernels (CUDA/HIP/Triton), inference serving optimization First-principles, resourceful, high EQ; customer-facing comfort On-site 5 days SF; must be in US