Senior DFT Engineer

Description We are hiring a Senior DFT Engineer in Europe to own Design-for-Test on customer SoCs end-to-end: DFT architecture, scan/ATPG, memory BIST, boundary scan, pattern validation and production test hand-off. The company provides end-to-end ASIC and COT design and turnkey manufacturing services to fabless companies and OEMs building advanced SoCs. Its offering covers architecture, RTL-to-GDSII implementation, analog/mixed-signal design, and productization through silicon, package, and test. Working across process nodes from 180nm to 2nm, it has completed over 350 tape-outs since 1986 Requirements Must-Have Requirements: BSc in Electrical Engineering from a recognized university. Minimum 3 years of hands-on DFT experience — must. Senior-level profiles preferred. DFT methodologies: scan, ATPG, at-speed test, memory BIST, I/O DFT. Scan insertion and ATPG for stuck-at, transition-delay, bridging and IDDQ fault models; test-coverage improvement. DFT DRC analysis and coverage debug with Synopsys DFT Compiler / TestMAX (TetraMAX) / SpyGlass DFT or equivalent Siemens (Mentor) Tessent tools. Memory BIST — Tessent MBIST. Strong knowledge of JTAG IEEE 1149.1, IEEE 1149.6 and IEEE 1500 (formerly P1500). Hands-on design and implementation of DFT features. End-to-end DFT flow ownership: concept → tape-out → production. Gate-level simulation setup and runs (pattern validation). Formal equivalence checking. Perl / Tcl / UNIX scripting for flow automation. Nice to Have Broader Siemens Tessent experience (ScanPro / TestKompress, LBIST) beyond MBIST. Advanced-node experience (7nm and below). Python for flow automation. Originally posted on Himalayas